Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch have achieved high memory cell densities. One of the simplest circuits for providing a small dynamic memory cell is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each cell employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line.
In also commonly assigned U.S. Pat. Nos. 3,811,076 by W. M. Smith, and 3,841,926, by R. A. Garnache and W. M. Smith, both filed on Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the hereinabove identified Dennard patent which utilizes a layer of doped polysilicon and an N+ diffusion region in a P type conductivity semiconductor substrate separated by a dielectric medium disposed on the surface of the semiconductor substrate for forming the storage capacitor of the cell. The polysilicon layer extends beyond the storage capacitor to act as a field shield between adjacent cells by applying a negative bias or fixed negative potential to the polysilicon layer. The N+ diffusion region of the storage capacitor is formed by using a doped segment of an insulating layer disposed on the surface of the semiconductor substrate and outdiffusing the dopant into the substrate.
In IBM Technical Disclosure Bulletin, Vol. 21, No. 9, February 1979, pp. 3823-3825, there is disclosed a one device memory cell which advantageously uses two layers of polysilicon.
Although the cells described hereinabove do provide memories having a high density of cells in a planar or two dimensional arrangement, yet each cell does require a significant given area of semiconductor surface. To reduce the size of the given area for each cell, structures have been made wherein the cell is formed in a three dimensional arrangement, such as described in commonly assigned U.S. Pat. No. 4,335,450, filed on Jan. 30, 1980, by D. R. Thomas, wherein there is disclosed a cell having a transistor disposed on a sidewall of a groove or trench with the storage node disposed below the transistor.
Also, commonly assigned U.S. Pat. No. 4,397,075, filed on July 3, 1980, by J. J. Fatula, Jr. and P. L. Garbarino, and commonly assigned U.S. patent application having Ser. No. 182,724, filed on Aug. 29, 1980, by S. A. Abbas and R. C. Dockerty, describe a dense, vertical cell having the storage capacitor in a well or trench. Somewhat similar cells are disclosed in U.S. Pat. No. 4,327,476, filed on Dec. 7, 1979, and in IBM Technical Disclosure Bulletins, February 1975, by G. V. Clarke and J. E. Tomko, pp. 2579-2580, July 1982, by C. G. Jambotkar, pp. 593-596, and February 1984, by B. El-Kareh, R. R. Garnache and F. R. White, pp. 4699-4701.
Furthermore, commonly assigned U.S. Pat. No. 4,462,040, filed on May 7, 1979, by I. T. Ho and J. Riseman discloses a one device dynamic random access memory utilizing a trench having vertical sidewalls with the storage capacitor and the transfer device located within the trench, and U.S. Pat. Nos. 4,271,418, filed Oct. 29, 1979, and 4,225,945, filed Oct. 29, 1979, teach a one device memory cell formed in a groove or trench with the storage node located at the bottom of the trench, the bit/sense line at the top of this substrate and the transfer device on the sidewall of the trench.